Many signal processing systems use multibit sigma delta modulators that include a quantizer to quantize an input signal into multiple bits. Generally, such quantizers consist of multiple comparators that are either based on a flash-type or tracking ADC (analog-to-digital converter) to deliver the multiple bits.
A fundamental problem with such multibit signal delta modulators is the so called offset error of the multiple comparators that are used in the quantizers for the quantization of the signal supplied. Such a comparator offset error can, for example, lead to the fact that for an input signal that lies just underneath the comparator threshold, the comparator output signal can assume a value that is stipulated for input signals lying above the comparator threshold. The reverse case is also conceivable. Comparator offset voltages represent the minimum DC input voltage that would have to be applied to input terminals of the comparator to cause the comparator to transition state.
The offset error can thus lead ultimately to the fact that under certain circumstances the comparator concerned comes to the incorrect decision. This error can affect the quality of the sigma delta modulators disadvantageously. This problem is particularly serious if the quantizer has multiple comparators in order to deliver a comparison result with multiple bit resolution. In this case not only does the offset error of a comparator as such possess relevance for the conversion quality, but so also does the fact that the individual offset errors of the majority of comparators differ from one another in an undefined manner. Thus, the comparator offset voltages can cause error in the comparator outputs, especially when the difference between the reference input signals adjacent comparators is small. This error offset error can restrict the speed at which these comparators can operate.
Traditional approach to reduce this offset error effect is to either increase device size of the comparator or by adding wideband high gain blocks before them. When the device size is increased it can reduce the maximum speed of operation of the comparator and hence can limit the speed of the overall multibit sigma delta modulators. This can also introduce huge kickback noise to a stage before the comparator. When the wideband high gain blocks are used before the comparators to suppress the offset problem, it can also significantly increase the power consumption. In addition, the parasitic poles of the wideband gain blocks may reduce the performance of the multibit sigma delta modulators. In most instances a trade off of the above two techniques are used. Another current approach requires reducing comparator clock speed to reduce the offset error. However, this can lead to a reduced speed of operation of the modulator and hence can lower the modulator performance.